tsmc cowos and advanced packaging

An AI accelerator is rarely one piece of silicon. It may combine a large logic die, smaller chiplets, and several stacks of high-bandwidth memory (HBM). Advanced packaging makes the short, dense electrical connections between those parts.

TSMC calls its main family of these packages Chip on Wafer on Substrate (CoWoS). The package places logic and memory on an interposer or redistribution layer, then mounts that assembly on a substrate that connects to the server board.¹

documented status as of september 2026

cowos-l: the 3.5-reticle-size version entered volume production in 2024 ²
larger package: tsmc certified a 5.5-reticle-size cowos solution in 2025 and planned volume production in 2026²
future scale: tsmc has described a roadmap beyond 14 reticles, not a product already in volume production³
main method: in july 2026, tsmc said large cowos remained its main advanced package for this work³
not disclosed: monthly cowos wafer capacity, customer allocation, package yield, and contract price

the parts of a cowos package

part	job
logic die or chiplets	perform arithmetic, control, and data movement
hbm stacks	store data close to the logic and provide a wide memory interface
interposer or redistribution layer	carry dense signals between logic and memory
through-silicon vias	carry signals vertically through silicon where the design uses them
package substrate	connect the dense package wiring to the larger circuit board

The word “2.5D” usually means that dies sit beside one another and communicate through a dense interconnection layer. In a 3D package, one active die can sit above another. A product can combine both methods, so the labels describe geometry rather than a strict sequence of better generations.

cowos variants

TSMC publishes three main CoWoS variants:¹

CoWoS-S uses a silicon interposer.
CoWoS-R uses an organic redistribution layer.
CoWoS-L uses a redistribution layer with local silicon interconnects where dense wiring is needed.

The choice changes package size, wiring density, cost, and manufacturing steps. It does not by itself determine application performance. That requires the complete logic, memory, network, power, cooling, and software design.

package size and reticles

A reticle is the patterned area that a lithography tool exposes at one time. Package descriptions such as “3.5 reticles” compare the interposer or connection area with that exposure field. They are not literal counts of processor dies.

TSMC’s 2025 annual report says its 3.5-reticle CoWoS-L technology entered its second year of volume production in 2025. The same report says TSMC completed certification of a 5.5-reticle solution in 2025 and would begin volume production in 2026.²

During TSMC’s July 2026 earnings call, an analyst referred to a roadmap beyond 14 reticles. TSMC said it was also developing a panel-based method called Chip on Panel on Substrate (CoPoS), but that large CoWoS packages remained the main supply and that panel production was still years away.³

manufacturing flow

A simplified flow is:

fabricate and test the logic and memory dies;
make the interposer or redistribution layer;
attach known-good dies with fine-pitch connections;
add underfill or molding material to protect the joints;
attach the assembly to the package substrate;
test power, signals, memory links, and thermal behavior.

Yield compounds across these steps. A bad logic die, memory stack, interposer, bond, or substrate can make the final package unusable. Known-good-die testing reduces that risk but cannot remove it.

capacity and supply claims

TSMC states that demand for advanced packaging has grown with AI and high-performance computing. It does not publish a monthly CoWoS wafer-capacity series in its annual report or quarterly calls. The 60,000, 120,000, and 140,000 wafer figures that circulated in industry reporting are estimates with different dates and definitions. This page does not present them as company guidance.

The same rule applies to claims about outsourced shares and package prices. TSMC works with substrate, assembly, and test suppliers, but a reported supplier share does not prove the allocation for one customer or accelerator.

broadcom xdsip is a separate platform

Broadcom’s 3.5D eXtreme Dimension System in Package (XDSiP) is Broadcom technology, not a TSMC CoWoS variant. Broadcom says the platform can combine more than 6,000 square millimeters of silicon and as many as 12 HBM stacks.⁴

The two technologies may appear in the same supply-chain discussion, but their published limits should not be merged. Nor does the existence of XDSiP prove that a named customer uses a particular foundry, package, or memory supplier.

what to record in a system comparison

For an advanced-package comparison, record:

the exact package variant and generation;
logic and memory dies, including HBM capacity and data rate;
interposer or redistribution-layer size;
package power and cooling method;
measured workload throughput and energy;
production status: sample, certified process, volume production, or shipping system.

Package area alone is not a performance benchmark.