sk hynix high-bandwidth memory
on this page
High-bandwidth memory (HBM) places several dynamic random-access memory (DRAM) dies in one vertical stack beside a processor. Thousands of short vertical connections move more data per second than a conventional memory bus can carry. AI accelerators use that bandwidth to keep their arithmetic units fed with model weights and intermediate results.
status as of september 2026
hbm3e: SK hynix began volume production of its 36 GB, 12-layer product in September 20241
hbm4: the company began mass shipments in the second quarter of 2026 and said production would rise during the second half2
next product: SK hynix shipped HBM4E samples during the first half of 2026 2
16-layer stack: the company displayed a 48 GB HBM4 product at CES and Computex 20263
evidence limit: customer allocation, yield, price, and market-share estimates are not product specifications
why hbm matters
A processor cannot use arithmetic capacity while it waits for data. HBM widens the path between memory and the processor, but it does not remove every bottleneck. Performance still depends on the model, arithmetic format, kernels, cache use, communication between processors, and the share of time spent outside matrix operations.
HBM is also a packaging problem. A system must place logic and several memory stacks on an interposer or another dense connection layer. More stacks can provide more capacity and bandwidth, but they also increase package size, heat, manufacturing steps, and the cost of a failed package.
current sk hynix products
| product | capacity | layers | documented status |
|---|---|---|---|
| hbm3e | 36 gb | 12 | volume production began september 2024 |
| hbm4 | 36 gb | 12 | mass shipments began in the second quarter of 2026 |
| hbm4 | 48 gb | 16 | displayed in 2026; development follows customer schedules |
| hbm4e | 48 gb display product | 12 | samples shipped in the first half of 2026 |
The status words matter. A sample lets a customer test a design. A prepared production system means the supplier is ready to build qualified parts. Volume production and mass shipment mean commercial units are moving. Earlier versions of this page treated these stages as interchangeable and gave an unsupported February 2026 production date.
hbm3e
SK hynix’s 12-layer HBM3E stacks twelve 3 GB DRAM dies for 36 GB total capacity. The company states a data rate of 9.6 gigabits per second per connection and aggregate bandwidth of 1.18 terabytes per second.1
The dies are 40% thinner than those in the prior eight-layer stack. Through-silicon vias carry signals vertically through the stack. SK hynix uses molded underfill between the dies to protect the connections, control warping, and move heat out of the package.
hbm4 and hbm4e
HBM4 doubles the interface from 1,024 to 2,048 connections. In September 2025, SK hynix said its 12-layer product operated above 10 gigabits per second per connection and had entered production preparation.4 Its July 2026 results supplied the later milestone: mass shipments began during the second quarter.2
At CES 2026, SK hynix displayed a 48 GB HBM4 stack made from sixteen dies. The product remained under development in line with customer schedules.3 At Computex, the company also displayed a 12-layer, 48 GB HBM4E product. A display is evidence that the part exists; it is not evidence of volume production.5
production and supply
SK hynix said in July 2026 that it had long-term agreements with about ten customers and was discussing more. It did not publish customer-by-customer allocation, HBM yield, or stack prices. The company also did not provide the monthly HBM wafer capacities that appeared in the old version of this page.2
Market-share estimates depend on whether a report counts units, bits, or revenue, and on the quarter measured. They are useful market estimates, but they should not be mixed with product specifications. This page therefore records the company’s shipping milestones and leaves point estimates to dated market reports.
implications for training systems
More bandwidth helps most when memory traffic is the limiting step. It does less when arithmetic, data loading, host work, or communication between accelerators controls throughput. Capacity and bandwidth are also different: capacity determines whether a model state fits, while bandwidth determines how quickly the processor can move stored data.
For a purchase or benchmark, record at least:
- the exact accelerator and HBM generation;
- memory capacity and reported bandwidth per device;
- arithmetic format, batch size, and sequence length;
- measured tokens per second and wall-clock time;
- power at the device or system boundary;
- software, driver, and kernel versions.
That information makes a comparison reproducible. “Uses HBM4” does not.
references
[2] SK hynix. (2026, July 29). Second-quarter 2026 financial results.
[3] SK hynix. (2026, January 5). SK hynix showcases next-generation AI memory innovations at CES 2026.
[4] SK hynix. (2025, September 12). SK hynix completes HBM4 development and readies mass production.
[5] SK hynix. (2026, June 2). Memory products shown at Computex 2026.